This invention relates to a memory system and more particularly to a command responsive memory circuit for providing multiple memory location data transfers in response to single command instructions.
Heretofore, memory operations included single memory location read and write cycles responsive to a single command. This was true whether separate buses were utilized for control signals and address signals, or whether a common bus was used for address signals and control signals with a separate bus for signal type identification. As a result of the single memory location per single command communications protocol, each memory data transfer required a separate data transfer command. In many applications where it was known in advance that multiple memory locations were to be sequentially transferred to the main processor of the data processing system, the single memory location per single command communications protocol increased control program size, increased operation time (that is, decreased benchmark performance) and unnecessarily complicated the structuring of the desired function. For example, where the contents of a multidigit register are to be transferred, for example, in a calculator, a separate read or write memory command was required for each digit position to be transferred.